The present invention relates to a shift register comprising an input, an output and a plurality of register cells serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer having an output coupled to the downstream register cell and a plurality of inputs.
The present invention further relates to an electronic device comprising such a shift register.
The present invention yet further relates to a method of controlling such a shift register.
The present invention still further relates to a software program product implementing such a control method.
Shift registers have become commonplace in digital electronic circuits. One of the most common uses of shift registers is to provide a serial to parallel or parallel to serial data conversion. For instance, data may be loaded into the shift register in parallel and shifted out of the shift register in a serial fashion, or alternatively, data may be shifted serially into a shift register, after which the data is read out in parallel.
The control of such a shift register can be efficiently implemented onto a controller such as a central processing unit (CPU), e.g. by means of software instructions as long as the data conversion level is maximal. A maximal data conversion level is achieved when the data does not require de-interleaving in case of parallel-to-serial conversion or interleaving in case of serial-to-parallel conversion, i.e. when for N-bit data the conversion is between N parallel channels and a single serial source.
However, in case of (de-)interleaving, such a controller typically requires a relative large number of instructions to implement the required data conversion. FIG. 1 shows an example of an arrangement in which data from serial shift register 10 has to be de-interleaved to two serial lanes 20 and 30, with the data from the odd register cells going to serial lane 20 and the data from the even register cells going to serial lane 30.
The problem is how to efficiently select the even and odd bits using a state of the art controller such as a RISC CPU instruction set. With normal shift register processing, every bit has to be shifted in and loaded separately. Thus for an M-bit word this requires M−1 shift instructions and m store instructions. For example, for M=32 this requires 32 loads+31 shifts=63 instructions to de-interleave the parallel data in the shift register 10. In high-speed application domains, the need to execute such a large number of instructions for the serial-to-parallel conversion or vice versa of a data word may cause an unacceptable degradation of the overall performance of the electronic device comprising the shift register.